北京凌峰伟业科技有限公司 (非本站正式会员)

北京凌峰伟业科技有限公司

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供应ADC08D1000CIYB,模数转换器ADC08D1000CIYB北京现货,ADC08D1000CIYB优势价格

  • 供应ADC08D1000CIYB,模数转换器ADC08D1000CIYB北京现货,ADC08D1000CIYB优势价格
产品价格:
电议/ 1pcs
交易说明:
北京现货,全新原装
厂 家:
NS
封 装:
LQFP128
批 号:
1206+
数 量:
100
 
点此询价

产品咨询直线:010-82059633

产品详细说明

 

制造商:  Texas Instruments    
RoHS: 
通道数量:  2    
结构:  Folding and Interpolating    
转换速率:  1000000 KSPs    
分辨率:  8 bit    
输入类型:  Differential    
信噪比:  48 dB    
接口类型:  Parallel, LVDS    
工作电源电压:  1.9 V    
最大工作温度:  + 85 C    
安装风格:  SMD/SMT    
封装 / 箱体:  LQFP EP    
最大功率耗散:  1600 mW   
最小工作温度:  - 40 C   
转换器数量:  2   
封装:  Tray   
工厂包装数量:  60   
电压参考:  Internal   

供应ADC08D1000CIYB,模数转换器ADC08D1000CIYB北京现货,ADC08D1000CIYB优势价格

 

说明

The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.4 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 2 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

特性

·         Internal Sample-and-Hold

·         Single +1.9V ±0.1V Operation

·         Choice of SDR or DDR Output Clocking

·         Interleave Mode for 2x Sampling Rate

·         Multiple ADC Synchronization Capability

·         Ensured No Missing Codes

·         Serial Interface for Extended Control

·         Fine Adjustment of Input Full-Scale Range and Offset

·         Duty Cycle Corrected Sample Clock

Key Specifications

·         Resolution: 8 Bits

·         Max Conversion Rate: 1 GSPS (min)

·         Bit Error Rate: 10-18 (typ)

·         ENOB @ 500 MHz Input: 7.4 Bits (typ)

·         DNL: ±0.15 LSB (typ)

·         Power Consumption

o    Operating: 1.6 W (typ)

o    Power Down Mode: 3.5 mW (typ)