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RM5261™64位微处理器与系统总线

RM5261™ Microprocessor with 64-Bit System Bus

特点
•双目录超标量微处理器
•200，250，266 MHz的工作频率
•320的Dhrystone2.1 MIPS
•高性能系统接口
•64位复用的地址/数据总线系统最佳的性能/价格
•高性能写入协议最大化非高速缓存写入带宽
•处理器时钟乘法器2，2.5，3，3.5，4，4.5，5个，6个，7个，8个，9个
•IEEE1149.1 JTAG边界扫描
•集成的片上高速缓存
•32KB指令和32KB数据 - 2路集联
•几乎索引，身体标记
•回写式和直写式上的每一个页面的基础上
•管道上重新启动的第一双数据缓存缺失
•集成的内存管理单元
•全相联联合TLB（I和D翻译共享）
•48个双项96页映射
•可变页面大小（4 KB到16 MB增量在4x）
•高性能浮点单元：高达530 MFLOPS
•单周期重复率常见的单精度运算和一些双精度
操作
•两个周期重复率的双精度乘法和双精度结合
乘加运算
•单周期重复率单精度乘加运算组合
•MIPS IV指令集
•浮点乘加指令增加在信号处理性能
和图形应用
•有条件的动作，以减少分支频率
•索引地址模式（寄存器+寄存器）
•嵌入式应用程序的增强
•专用DSP整数乘法累加指令和三操作数乘
指令
•I和D通过设置缓存锁定
•可选的专用异常向量中断
•全静态0.25微米CMOS设计，带功率下降逻辑
•待机功耗模式，减少等待指令
•2.5 V与3.3 V IO的核心
•208引脚PQFP封装
Features
• Dual Issue superscalar microprocessor
• 200, 250, 266 MHz operating frequencies
• 320 Dhrystone 2.1 MIPS
• High-performance system interface
• 64-bit multiplexed system address/data bus for optimum price/performance
• High-performance write protocols maximize uncached write bandwidth
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• IEEE 1149.1 JTAG boundary scan
• Integrated on-chip caches
• 32KB instruction and 32KB data — 2 way set associative
• Virtually indexed, physically tagged
• Write-back and write-through on a per page basis
• Pipeline restart on first doubleword for data cache misses
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 48 dual entries map 96 pages
• Variable page size (4 KB to 16 MB in 4x increments)
• High-performance floating-point unit: up to 530 MFLOPS
• Single cycle repeat rate for common single-precision operations and some double-precision
operations
• Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
• Single cycle repeat rate for single-precision combined multiply-add operation
• MIPS IV instruction set
• Floating point multiply-add instruction increases performance in signal processing
and graphics applications
• Conditional moves to reduce branch frequency
• Index address modes (register + register)
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
• I and D cache locking by set
• Optional dedicated exception vector for interrupts
• Fully static 0.25 micron CMOS design with power down logic
• Standby reduced power mode with WAIT instruction
• 2.5 V core with 3.3 V IOs
• 208-pin PQFP package
硬件概述
RM5261提供一个高层次的针对高性能嵌入式应用的整合。

Hardware Overview
The RM5261 offers a high-level of integration targeted at high-performance embedded applications.