- IC型号
深圳市金霖电子商行(原深圳市鸿成电子)
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- 联系人:李先生
- 电话:0755-18929391685
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- 手机:18929390689/18929391685
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供应MC100E131FNR2,原装柜台现货MC100E131FN,价格优势
- 产品价格:
- ¥30/ 1pcs
¥25/ 10pcs
¥15/ 100pcs
¥15/ 1k
¥15/ 10k
- 交易说明:
- 全新原装,柜台现货,价格优势,欢迎咨询
- 配送说明:
- 全新原装,柜台现货,价格优势,欢迎咨询
- 厂 家:
- ON
- 封 装:
- PLCC
- 批 号:
- 01+
- 数 量:
- 2500
产品咨询直线:0755-18929391685
产品详细说明
安森美半导体5V的ECL4位D触发器
ON Semiconductor [5V ECL 4-Bit D Flip-Flop]特点•1100 MHz最小。切换频率
•差分输出
•个人和共同时钟
•个人复位(异步)
•配对集(异步)
•PECL模式经营范围:VCC= 4.2 V到5.7 VEE=0 V
•NECL模式经营范围:VCC= 0 V,VEE=-4.2 V至-5.7 V
•亚稳态的时间常数为200 ps。
•内部输入50 K?下拉电阻
•ESD保护:人体模型;> 2千伏,机器模型> 200 V
•达到或超过JEDEC的规格EIA/JESD78 IC闭锁试验
•湿度敏感度等级:
PB= 1
无铅= 3
有关其他信息,请参阅应用笔记AND8003/ D
•可燃性等级:UL94 V-0@0.125中,
氧指数:28〜34
•晶体管数量= 240设备
•Pb-Free包可以*
描述
MC10E/100E131是一个四主从D型触发器与差分输出。每个触发器时钟可分别由持有共同的时钟(CC)低和使用时钟使能(CE)输入时钟。公共时钟是通过持有的CE投入低和使用CC所有四个触发器的时钟。在这种情况下,执行共同的时钟控制的功能的CE输入,
每个触发器。
异步复位个人(R)。异步设置控制(S)在对一起勾结,与配对选择反映物理芯片对称性。
数据进入主当CC和CE低,传输的奴隶时,CC或CE(或两者)去高。
该100系列包含温度补偿。
Features
• 1100 MHz Min. Toggle Frequency
• Differential Outputs
• Individual and Common Clocks
• Individual Resets (asynchronous)
• Paired Sets (asynchronous)
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
• Metastability Time Constant is 200 ps.
• Internal Input 50 k Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 240 devices
• Pb−Free Packages are Available*
The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock, to
each flip-flop.
Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and CE are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.
The 100 Series contains temperature compensation.