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EATURES
APPLICATIONS
DESCRIPTION
CDCM61002
www.ti.com.................................................................................................................................................... SCAS870B–FEBRUARY 2009–REVISED JULY 2009
Two Output, Integrated VCO, Low-Jitter Clock Generator
• Chip Enable Control Pin Available
2• One Single-Ended/Crystal Reference Input • 3.3-V Core and I/O Power Supply
Including 24.8832 MHz, 25 MHz, and • Industrial Temperature Range: –40°C to +85°C
26.5625 MHz
• 5-mm × 5-mm, 32-pin, QFN (RHB) Package
• Input Frequency Range: 21.875 MHz to
• ESD Protection Exceeds 2 kV (HBM)
28.47 MHz
• On-Chip VCO Operates in Frequency Range of
1.75 GHz to 2.05 GHz
• Low Jitter Clock Driver for High-End Datacom
• 2x Output Available: Applications Including SONET, Ethernet, Fibre
– Pin-Selectable Between LVPECL, LVDS, or Channel, Serial ATA, and HDTV
2-LVCMOS; Operates at 3.3 V • Cost-Effective High-Frequency Crystal
Oscillator Replacement
• LVCMOS Bypass Output Available
• Output Frequency Selectable by /1, /2, /3, /4, /6,
/8 from a Single Output Divider
• Supports Common LVPECL/LVDS Output
The CDCM61002 is a highly versatile, low-jitter
Frequencies:
frequency synthesizer that can generate two low-jitter
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
clock outputs, selectable between low-voltage
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
positive emitter coupled logic (LVPECL), low-voltage
155.52 MHz, 156.25 MHz, 159.375 MHz, differential signaling (LVDS), or low-voltage
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, complementary metal oxide semiconductor
311.04 MHz, 312.5 MHz, 622.08 MHz, (LVCMOS) outputs, from a low-frequency crystal or
625 MHz LVCMOS input for a variety of wireline and data
communication applications. The CDCM61002
• Supports Common LVCMOS Output
features an onboard PLL that can be easily
Frequencies:
configured solely through control pins. The overall
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz, output random jitter performance is less than 1ps,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz, RMS (from 10 kHz to 20 MHz), making this device a
155.52 MHz, 156.25 MHz, 159.375 MHz, perfect choice for use in demanding applications such
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz as SONET, Ethernet, Fibre Channel, and SAN. The
CDCM61002 is available in a small, 32-pin, 5-mm ×
• Output Frequency Range: 43.75 MHz to
5-mm QFN package.
683.264 MHz (See Table 3)
• Internal PLL Loop Bandwidth: 400 kHz
• High-Performance PLL Core:
– Phase Noise typically at –146 dBc/Hz at
5-MHz Offset for 625-MHz LVPECL Output
– Random Jitter typically at 0.509 ps, RMS
(10 kHz to 20 MHz) for 625-MHz LVPECL
Output
• Output Duty Cycle Corrected to 50% (± 5%)
• Low Output Skew of 20 ps on LVPECL Outputs
• Divider Programming Using Control Pins:
– Two Pins for Prescaler/Feedback Divider
– Three Pins for Output Divider
– Two Pins for Output Select