深圳市四海恒通科技有限公司 （非本站正式会员）

AX1251  1A吸入/源出总线终端稳压器

性能描述：

        The AX1251 is a simple, cost-effective  and high-speed linear regulator designed to generate termination voltage in double data rate  (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific  interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator  is capable of actively  sinking or sourcing up to 1A while regulating an  output voltage to within 20mV.  The output termination voltage cab be tightly regulated to track 1/2VDDQ by two  external voltage divider resistors or the desired output voltage can be pr ogrammed by externally forc ing the REFEN pin voltage.
        The AX1251 also incorporates a high-speed differential ampl ifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in  bi-directions and on-chip thermal shut-down protection.
        The AX1251 is available in the SOT23-5L surface mount package.